Assembly and Reliability of a Wafer Level CSP

Category: Chip Scale Package (CSP)
Post Date: July 20, 2004
Author(s): Parvez M Patel, Motorola, Libertyville, IL; Anthony Primavera, PhD, Universal Instruments Corporation, Binghamton, NY; and K. Srihari, PhD, State University of New York, Binghamton

Description
A significant advantage of the chip-size package is that it can be made directly on the wafer, since each CSP covers only its individual chip site. Using this approach, each "package" is assembled to the corresponding IC while still on the wafer. The ICs can be burned-in and tested before being diced into individual, fully furnished packages. This paper describes research aimed at illuminating assembly and reliability issues concerning such wafer-level CSPs.